Efficient hybrid continuous-time/discrete-time cascade ΣΔ modulators for wideband applications

This paper analyses the use of hybrid continuous-time/discrete-time cascade Σ∆ modulators for the implementation of power-efficient analog-to-digital converters in broadband wireless communication systems. Two alternative implementations of multi-rate cascade architectures are studied and compared with conventional single-rate continuous-time topologies, taking into account the impact of main circuit-level error mechanisms, namely: mismatch, finite dc gain and gainbandwidth product. In all cases, closed-form design equations are derived for the nonideal in-band noise power of all Σ∆ modulators under study, providing analytical relationships between their system-level performance and the corresponding circuit-level error parameters. Theoretical predictions match simulation results, showing that the lowest performance degradation is obtained by a new kind of multi-rate hybrid Σ∆ modulator, in which the front-end (continuous-time) stage operates at a higher rate than the back-end (discrete-time) stages. As a case study, the design of a hybrid GmC/switched-capacitor fourth-order (two-stage, 4bit) cascade Σ∆ modulator is discussed to illustrate the potential benefits of the presented approach1.